View KH232AK_4616143.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

www.cadeka.com
KH232
Low Distortion Wideband Op Amp
Features
s s s s s s s
General Description
The KH232 is a wideband low distortion operational amplifier designed specifically for high speed, low gain applications requiring wide dynamic range. Utilizing a current feedback architecture, the KH232 offers high speed performance while maintaining DC precision. The KH232 offers precise gains from 1 to 5 with a true 0.1% linearity and provides stable, oscillationfree operation across the entire gain range without external compensation. The KH232, a pin compatible enhanced version of the KH231, reduces 2nd and 3rd harmonic distortion to an extremely low -69dBc at 20MHz (2Vpp, RL = 100). Additional features provided by the KH232 include a small signal bandwidth of 270MHz, a large signal bandwidth of 95MHz and a 3000V/s slew rate. The input offset voltage is typically 1mV with an input offset drift of 10V/C. The KH232 combines these high performance features with its 0.05% settling time of 15ns and its 100mA drive capability to provide high speed, high resolution A/D and D/A converter systems with an attractive solution for driving and buffering. Wide dynamic range systems such as radar and communication receivers requiring low harmonic distortion and low noise will find the KH232 to be an excellent choice. As a line driver, the KH232 set at a gain of 2 cancels matched line losses. The KH232 is constructed using thin film resistor/bipolar transistor technology, and is available in the following versions:
Supply Voltage
-69dBc 2nd and 3rd harmonics at 20MHz -3dB bandwidth of 270MHz 0.05% settling in 15ns 3000V/s slew rate 1mV input offset voltage, 10V/C drift 10V, 100mA max output Direct replacement for CLC232
Applications
s s s s s s s
Flash A/D drivers DAC current-to-voltage conversion Wide dynamic range IF amps VCO drivers DDS postamps Radar/communication receivers Precision line drivers
Bottom View
ICC Adjust Case ground GND 7 Adjust -VCC 8 9 -VCC V+ 6 10 Collector Supply Output
KH232AI KH232AK KH232AM
-25C to +85C -55C to +125C -55C to +125C
Non-Inverting Input Inverting Input Not Connected
+
V- 5 NC 4 3 Case ground GND 2
4 4
-
11 Vo 12 +VCC
Collector Supply
1 Supply Voltage
KH232HXC KH232HXA
-55C to +125C -55C to +125C
12-pin TO-8 can 12-pin TO-8 can, features burn-in & hermetic testing 12-pin TO-8 can, environmentally screened and electrically tested to MIL-STD-883 SMD#: 5962-9166501HXC SMD#: 5962-9166501HXA
Adjust +VCC ICC Adjust
Typical Performance
Gain Setting Parameter 1 2 5 -1 -2 -5 Units MHz ns V/ns ns -3dB bandwidth 430 270 135 220 175 110 rise time (2V) 1.8 2.0 2.5 2.0 2.2 2.9 slew rate 2.5 3.0 3.0 3.0 3.0 3.0 settling time (to 0.1%) 12 12 12 12 12 15
Pins 2 and 8 are used to adjust the supply current or to adjust the offset voltage (see text). These pins are normally left unconnected.
REV. 1A January 2004
DATA SHEET
KH232
KH232 Electrical Characteristics
PARAMETERS Ambient Temperature Ambient Temperature FREQUENCY DOMAIN RESPONSE | -3dB bandwidth (note 2) large-signal bandwidth gain flatness (note 2) peaking peaking rolloff group delay linear phase deviation reverse isolation non-inverting inverting KH232AI
(TA = +25C, Av = +2V, VCC = 15V, RL = 100, Rf = 250; unless specified) TYP +25C +25C 270 165 95 0.1 0.1 0.4 3.5 0.5 0.5 53 36 MIN & MAX RATINGS -25C -55C >200 >145 >80 <0.6 <1.5 <0.6 - <2.0 >43 >26 <2.4 <7.0 - <22 <15 >2.5 - <-64 <-64 <3.2 <23 <2.6 <-154 <64 <64 <4.0 <25 <29 <125 <31 <200 >45 >40 <27 >100 <2.5 - >11 +25C +25C >200 >145 >80 <0.3 <0.3 <0.6 - <2.0 >43 >26 <2.3 <6.5 - <17 <10 >2.5 - <-64 <-64 <3.2 <23 <2.6 <-154 <64 <64 <2.0 <25 <21 <125 <15 <200 >45 >40 <27 >200 <2.5 - >11 +85C +125C >200 >120 >60 <0.6 <0.8 <1.0 - <2.0 >43 >26 <2.7 <6.5 - <22 <15 >1.8 - <-56 <-64 <3.5 <25 <2.9 <-153 <72 <72 <4.5 <25 <31 <125 < 35 <200 >45 >40 <29 >400 <2.5 - >11 MHz MHz MHz dB dB dB ns dB dB ns ns ns ns % V/ns ns dBc dBc SSBW SSBW FPBW GFPL GFPH GFR GD LPD RINI RIIN TRS TRL TS TSP OS SR OR HD2 HD3 UNITS SYM
CONDITIONS KH232AK/AM/HXC/HXA Vo 0.63Vpp Vo 2Vpp Vo 10Vpp Vo 0.63Vpp 0.1 to 50MHz >50MHz at 100MHz to 100MHz to 100MHz
| | |
TIME DOMAIN RESPONSE rise and fall time settling time to 0.05% to 0.1% overshoot slew rate (overdriven input) overload recovery <50ns pulse, 200% overdrive NOISE AND DISTORTION RESPONSE | 2nd harmonic distortion | 3rd harmonic distortion equivalent input noise voltage inverting current non-inverting current noise floor integrated noise integrated noise STATIC, DC PERFORMANCE * input offset voltage average temperature coefficient * input bias current average temperature coefficient * input bias current average temperature coefficient * power supply rejection ratio common mode rejection ratio * supply current MISCELLANEOUS PERFORMANCE non-inverting input resistance non-inverting input capacitance output impedance output voltage range
2V step 10V step 5V step 2.5V step 5V step <1% error
2.0 5.0 15 12 5 3.0 120
2Vpp, 20MHz 2Vpp, 20MHz >100kHz >100kHz >100kHz >100kHz 1kHz to 200MHz 5MHz to 200MHz
-69 -69 2.8 20 2.3 -155 57 57 1 10 5.0 50 10 125 50 46 25 400 1.3 5, 37 12
VN nV/Hz ICN pA/Hz pA/Hz NCN dBm(1Hz) SNF Vrms INV Vrms INV mV V/C A nA/C A nA/C dB dB mA k pF , nH V VIO DVIO IBN DIBN IBI DIBI PSRR CMRR ICC RIN CIN RO VO
non-inverting inverting
no load DC @ 100MHz no load
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters.
Absolute Maximum Ratings
VCC Io common mode input voltage, Vo differential input voltage thermal resistance junction temperature operating temperature storage temperature lead temperature (soldering 10s) 20V 100mA |VCC| >15V (30-|VCC|)V |VCC| 15V |VCC|V 3V (see thermal model) +175C AI: -25C to +85C AK/AM/HXC/HXA: -55C to +125C -65C to +150C +300C
Recommended Operating Conditions
VCC Io common mode input voltage gain range note 1: * | 5V to 15V 75mA (|VCC| -5)V 1 to 5
note 2:
AI/AK/AM/HXC/HXA 100% tested at +25C AK/AM/HXC/HXA 100% tested at +25C and sample tested at -55C and +125C | AI sample tested at +25C The output amplitude used in testing is 0.63Vpp. Performance is guaranteed for conditions listed.
2
REV. 1A January 2004
KH232
DATA SHEET
KH232 Typical Performance Characteristics (T
Non-Inverting Frequency Response Normalized Magnitude (1dB/div) Normalized Magnitude (1dB/div)
Gain Av = 1 Gain
A
= +25C, Av = +2, VCC = 15V, RL = 100, Rf = 250; unless specified)
Settling Time vs. CL
35
Rs
Inverting Frequency Response
70
CL Av = +2
Av = -2
30
Phase Av = 5
Phase
Settling Time (ns)
Av = 2
1k
60 50
Phase (45 deg/div)
Phase (45 deg/div)
25
RS
RS ()
Av = -5 Av = -5 Av = -2 Av = -1
Av = -1
20
TS
40 30 20 10 0 100 1000
Av = 5 Av = 2 Av = 1
15 10 5
0
150
300
0
150
300
Frequency (MHz) Bandwidth vs. VCC
1.2
Frequency (MHz)
CL (pF)
K
Frequency Response vs. RL
RL = 500
K
Large Signal Non-Inverting Gain & Phase
Gain Av = 2 Vo = 10Vpp
Relative Bandwidth
1.0
RL = 200 Pins 1 and 2 Shorted Pins 8 and 9 shorted
Phase (45 deg/div)
(1dB/div)
0.8
RL = 50
RL = 100
(1dB/div)
0
Phase
0.6
Av = 2
0.4 4 6 8 10 12 14 16 0 150 300 150 300
VCC (V) 2nd Harmonic Distortion
-20 -30
Frequency (MHz)
Frequency (MHz)
K
3rd Harmonic Distortion
-20 -30
K
-40 -45 -50
2nd and 3rd Harmonic DistortionK
Vo = 2Vpp
Distortion (dBc)
Distortion (dBc)
-40
8Vpp
-40
8Vpp
Distortion (dBc)
-55 -60 -65 -70 -75 -80 -85 -90
2nd
-50
4Vpp
-50
4Vpp
-60 -70
2Vpp
-60 -70
2Vpp
3rd
-80
1Vpp
-80
1Vpp
-90 1 10 100
-90 1 10 100
1
10
100
Frequency (Hz) 2-Tone, 3rd Order Intermod. Intercept K
50 100
50 Pout
Frequency (Hz) Equivalent Input Noise
Frequency (MHz)
K
100 50
CMRR and PSRR
PSRR
Noise Voltage (nV/Hz)
45
Noise Current (pA/Hz)
Interdept Point (dBm)
PSRR/CMRR (dB)
50
40 35 30 25 20 15 0 10 20 30 40 50 60 70 80 90 100
Inverting Current 20pA/Hz
CMRR
40 30 20 10
10
10
Voltage 2.8nV/Hz Non-Inverting Current 2.3pA/Hz
1 100 1k 10k 100k 1M 10M
1 100M
1
10
100
1k
10k
100k
1M
10M 100M
Frequency (MHz) Small Signal Pulse Response Output Voltage (400mV/div)
Frequency (Hz) Large Signal Pulse Response
Frequency (Hz)
K
Settling Time
0.20 0.15
K
Output Voltage (2V/div)
Settling Error (%)
Av = 2
Av = 2
0.10 0.05 0 -0.05 -0.10 -0.15 -0.20
5ns/div
50ns/div
Av = -2
Av = -2
Time (5ns/div)
Time (5ns/div)
Time (ns)
K
REV. 1A January 2004
K
K
3
DATA SHEET
KH232
Operation The KH232 is based on the current feedback op amp topology, a design that uses current feedback instead of the usual voltage feedback. The use of the KH232 is basically the same as that of the conventional op amp (see Figures 1 and 2). Since the device is designed specifically for low gain applications, the best performance is obtained when the circuit is used at gains between 1 and 5. Additionally, performance is optimum when a 250 feedback resistor is used.
Layout Considerations To assure optimum performance the user should follow good layout practices which minimize the unwanted coupling of signals between nodes. During initial breadboarding of the circuit use direct point to point wiring, keeping the lead lengths to less than 0.25". The use of solid, unbroken ground plane is helpful. Avoid wire-wrap type pc boards and methods. Sockets with small, short pin receptacles may be used with minimal performance degradation although their use is not recommended. During pc board layout keep all traces short and direct The resistive body of Rg should be as close as possible to pin 5 to minimize capacitance at that point. For the same reason, remove ground plane from the vicinity of pins 5 and 6. In other areas, use as much ground plane as possible on one side of the board. It is especially important to provide a ground return path for current from the load resistor to the power supply bypass capacitors. Ceramic capacitors of 0.01 to 0.1f (with short leads) should be less than 0.15 inches from pins 1 and 9. Larger tantalum capacitors should be placed within one inch of these pins. VCC connections to pins 10 and 12 can be made directly from pins 9 and 1, but better supply rejection and settling time are obtained if they are separately bypassed as in figures 1 and 2. To prevent signal distortion caused by reflections from impedance mismatches, use terminated microstrip or coaxial cable when the signal must traverse more than a few inches. Since the pc board forms such an important part of the circuit, much time can be saved if prototype boards of any high frequency sections are built and tested early in the design phase. Evaluation boards designed for either inverting or non-inverting gains are available. Offset Voltage Adjustment If trimming of the input offset voltage (Vos = Vni -Vin) is desired, a resistor value of 10k to 1M placed between pins 8 and 9 will cause Vos to become more negative by 8mV to 0.2mV respectively. Similarly, a resistor placed between pins 1 and 2 will cause Vos, to become more positive. Thermal Considerations At high ambient temperatures or large internal power dissipations, heat sinking is required to maintain acceptable junction temperatures. Use the thermal model on the previous page to determine junction temperatures. Many styles of heat sinks are available for TO-8 packages; the Thermalloy 2240 and 2268 are good examples. Some heat sinks are the radial fin type which cover the pc board and may interfere with external components. An excellent solution to this problem is to use surface mounted resistors and capacitors. They have a very low profile and actually improve high frequency performance. For use of these heat sinks with conventional components, a 0.1" high spacer can be inserted under the TO-8 package to allow sufficient clearance.
REV. 1A January 2004
+15V 3.9
33 0.1
6 1 12 11 10 3,7 9
.01 Capactance in F
Vin Ri 49.9 Rg
+ -
KH232
5
Vo 250 RL 100
-15V 3.9
33 0.1 .01
A v = 1+
Rf Rg
Rf = 250
Figure 1: Recommended non-inverting gain circuit
+15V 3.9
33 0.1 100 Rg
6 1 12 11 10 3,7 9
.01 Capactance in F
+ -
KH232
5
Vo 250 RL 100
Vin Ri
-15V 3.9
33 0.1 .01
Rf Av = - Rg Rf = 250 For Zin = 50, select Rg || Ri = 50
Figure 2: Recommended inverting gain circuit
4
KH232
DATA SHEET
Tcase 100C/W Tj(pnp) Ppnp 100C/W Tj(npn) Pnpn 48C/W Tj(circuit) Pcircuit + Tambient ca
Other methods of heat sinking may be used, but for best results, make contact with the base of the KH232 package, use a large thermal capacity heat sink and use forced air convection. Low VCC Operation: Supply Current Adjustment The KH232 is designed to operate on supplies as low as 5V. In order to improve full bandwidth at reduced supply voltages, the supply current (ICC) must be increased. The plot of Bandwidth vs. VCC, shows the effect of shorting pins 1 and 2 and pins 8 and 9; this will increase both bandwidth and supply current. Care should be taken to not exceed the maximum junction temperatures; for this reason this technique should not be used with supplies exceeding 10V. For intermediate values of VCC, external resistors between pins 1 and 2 and pins 8 and 9 can be used.
P(circuit) = (ICC)((+VCC) - (VCC)) where ICC = 14mA at 15V P(xxx) = [(VCC) - Vout - (Icol) (Rcol + 4)] (Icol) (%Duty) For positive Vo and VCC, this is the power in the npn device. For negative Vo and VCC, this is the power in the pnp device. Icol = Vo/RL or 12mA, whichever is greater. (Include feedback R in RL.) Rcol is a resistor (33 recommended) between the xxx collector and VCC. The limiting factor for output current and voltage is junction temperature. Of secondary importance is I(out), which should not exceed 150mA. Tj(pnp) = P(pnp) (100 + ca) + (P(cir) + P(npn))(ca) + Ta, similar for Tj(npn). Tj(cir) = P(cir)(48 + ca) + (P(pnp) + P(npn))(ca) + Ta. ca = 65C/W for the KH232 without heat sink in still air. 35C/W for the KH232 with a Thermalloy 2268A heat sink in still air. 15C/W for the KH232 with a Thermalloy 2268A heat sink at 300 ft/min air. (Thermalloy 2240A works equally as well.) For example, with the KH232 operating at 15V while driving a 100 load at 15Vpp output (50% duty cycle pulse waveform, DC = 0), P(npn) = P(pnp) = 190mW (Rcol = 33) and P(cir) = 0.42W. Then with the Thermalloy 2268 heat sink and air flow of 300 ft/min the output transistors' Tj is 31C above ambient and worst case Tj in the rest of the circuit is 32C above ambient. In still air, however, the rise in Tj is 47C and 48C, respectively. With no heat sink, the rise in Tj is 71C and 72C, respectively! Under most conditions, HEAT SINKING IS REQUIRED.
REV. 1A January 2004
5
DATA SHEET
KH232
KH232 Package Dimensions
A L e1 e2
7 6 8 9 10 11 12
D
D1
e
5 4
b F
k
3 2 1
k1
TO-8
SYMBOL
A b D D1 e e1 e2 F k k1 L
INCHES
Minimun 0.142 0.016 0.595 0.543 Maximum 0.181 0.019 0.605 0.555
MILIMETERS
Minimum 3.61 0.41 15.11 13.79 Maximum 4.60 0.48 15.37 14.10
NOTES: Seal: cap weld Lead finish: gold per MIL-M-38510 Package composition: Package: metal Lid: Type A per MIL-M-38510
0.400 BSC 0.200 BSC 0.100 BSC 0.016 0.026 0.026 0.310 0.030 0.036 0.036 0.340
10.16 BSC 5.08 BSC 2.54 BSC 0.41 0.66 0.66 7.87 0.76 0.91 0.91 8.64
45 BSC
45 BSC
Life Support Policy Cadeka's products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of Cadeka Microcircuits, Inc. As used herein: 1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Cadeka does not assume any responsibility for use of any circuitry described, and Cadeka reserves the right at any time without notice to change said circuitry and specifications.
www.cadeka.com
(c) 2004 Cadeka Microcircuits, LLC

▲Up To Search▲

Price & Availability of KH232AK

	To Download KH232AK Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .